Direct mapping of strain in silicon MOSFET by TEM

Saturday 17 April 2010

Strained silicon is an integral feature of the present generation of transistors because of the associated enhancement in carrier mobility.

Strain can be obtained by various methods. One consists in stressors introduced in the CMOS component, such as SiGe (silicon germanium alloy) source and drain, leading to a compressive uniaxial stress of the Si channel, or SiN (silicon nitride) layers surrounding the transistor gate giving tensile or compressive strain depending on the SiN stress. Strain can be measured by Raman spectrometry or electron microscopy, coupling HRTEM and GPA. The nanoelectronic team has access to up-to-date devices allowing strain measurements at various scales (down to the nanometer scale). Recently, a specific technique (Hollow Dark) has been developed and patented, which allows both strain measurement and imaging over a large field of view (hundreds of microns), with a sub-nanometer resolution [see picture].
JPEG - 64.2 kb

Further readings : - Direct mapping of strain in a strained silicon transistor by high-resolution electron microscopy Hue, F; Hytch, M; Bender, H, et al. Phys. Rev. Lett. 100, 156602 (2008)
- Nanoscale holographic interferometry for strain measurements in electronic devices, Hytch M, Houdellier F, Hue F, et al. Nature 453, 1086 (2008)


Nano is: